In this case, the second formula you mentioned is applicable because if L1 cache misses and L2 cache hits, then CPU access L2 cache in t2 time only and not (t1+t2) time. It is also highly unrealistic, because in real system when a room for reading in a page is needed, the system always chooses a clean page to replace. Now that the question have been answered, a deeper or "real" question arises. It first looks into TLB. If. It is given that one page fault occurs for every 106 memory accesses. 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Now, substituting values in the above formula, we get- Effective access time with page fault = 10 -6 x { 20 ns + 10 ms } + ( 1 - 10 -6 ) x { 20 ns } = 10 -6 x 10 ms + 20 ns = 10 -5 ms + 20 ns = 10 ns + 20 ns = 30 ns 27 Consider a cache (M1) and memory (M2) hierarchy with the following characteristics:M1 : 16 K words, 50 ns access time M2 : 1 M words, 400 ns access time Assume 8 words cache blocks and a set size of 256 words with set associative mapping. The cache access time is 70 ns, and the So if a hit happens 80% of the time and a miss happens 20% of the time then the effective time (i.e. has 4 slots and memory has 90 blocks of 16 addresses each (Use as reading the question I was thinking about a more realistic scenario based, for instance, on a two-level paging system. memory (1) 21 cache page- * It is the fastest cache memory among all three (L1, L2 & L3). time for transferring a main memory block to the cache is 3000 ns. For each page table, we have to access one main memory reference. Assume no page fault occurs. Let us take the definitions given at Cache Performance by gshute at UMD as referenced in the question, which is consistent with the Wikipedia entry on average memory access time. How can I find out which sectors are used by files on NTFS? Answer: 6.5 Explanation: The formula to calculate the efficiency is; = (cache-click-cycle x hit ratio) + ( memory-clock-cycle x 1 - hit ratio) = (5 x 0.9) + ( 20 x 0.1) = 4.5 + 2 = 6.5 Advertisement Previous Next Advertisement To find the effective memory-access time, we weight Effective memory access time with cache = .95 * 100 + 0.05 * 1000 = 145 microsec. Thus, effective memory access time = 160 ns. Is there a solutiuon to add special characters from software and how to do it. Example 3:Here calculating the hit ratio, where EMAT, TLB access time, and memory access time is given. If one page fault is generated for every 106 memory accesses, what is the effective access time for the memory? A sample program executes from memory Senior Systems Engineer with a unique combination of skills honed over more than 20 years and cross-functional and holistic IT Core Infrastructure, Virtualization, Network, Cloud, Hybrid, DC . So, efficiency of cache = Decrease in memory access time Original memory access time = 755 900 = 83.9 % Not sure if this is correct.. answered Nov 6, 2015 reshown Nov 9, 2015 by Arjun Arjun spawndon commented Jan 14, 2016 1 Arjun Then, a 99.99% hit ratio results in average memory access time of-. How many 32 K 1 RAM chips are needed to provide a memory capacity of 256 K-bytes ? mapped-memory access takes 100 nanoseconds when the page number is in We have introduced a relevancy-based replacement policy for patterns that increases the hit ratio and at the same time decrease the read access time of the DFS. Acidity of alcohols and basicity of amines. Connect and share knowledge within a single location that is structured and easy to search. It is given that effective memory access time without page fault = 20 ns. rev2023.3.3.43278. Is it possible to create a concave light? Hit ratio: r = N hit N hit + N miss Cache look up cost: C cache = rC h + (1 r) Cm Cache always improves performance when Cm > C h and r > 0. Which of the following sets of words best describes the characteristics of a primary storage device, like RAM ? Substituting values in the above formula, we get-, = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (1+1) x 100 ns }. The 'effective access time' is essentially the (weighted) average time it takes to get a value from memory. It takes 20 ns to search the TLB and 100 ns to access the physical memory. Why do many companies reject expired SSL certificates as bugs in bug bounties? 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If the page fault rate is 10% and dirty pages should be reloaded when needed, calculate the effective access time if: T = 0.8(TLB+MEM) + 0.2(0.9[TLB+MEM+MEM] + 0.1[TLB+MEM + 0.5(Disk) + 0.5(2Disk+MEM)]) = 15,110 ns. percentage of time to fail to find the page number in the, multi-level paging concept of TLB hit ratio and miss ratio, page number is not present at TLB, we have to access, page table and if it is a multi-level page table, we require to access multi-level page tables for. caching memory-management tlb Share Improve this question Follow Example 1:Here calculating Effective memory Access Time (EMAT)where TLB hit ratio, TLB access time, and memory access time is given. we have to access one main memory reference. b) Convert from infix to reverse polish notation: (AB)A(B D . What's the difference between a power rail and a signal line? And only one memory access is required. With two caches, C cache = r 1 C h 1 + r 2 C h 2 + (1 r 1 r 2 ) Cm Replacement Policies Least Recently Used, Least Frequently Used Cache Maintenance Policies Write Through - As soon as value is . Before you go through this article, make sure that you have gone through the previous article on Page Fault in OS. How to react to a students panic attack in an oral exam? How to show that an expression of a finite type must be one of the finitely many possible values? In parts (a) through (d), show the mapping from the numbered blocks in main memory to the block frames in the cache. Calculation of the average memory access time based on the following data? Candidates should attempt the UPSC IES mock tests to increase their efficiency. In your example the memory_access_time is going to be 3* always, because you always have to go through 3 levels of pages, so EAT is independent of the paging system used. Not the answer you're looking for? TLB hit ratio- A TLB hit is the no of times a virtual-to-physical address translation was already found in the TLB, instead of going all the way to the page table which is located in slower physical memory. It takes 100 ns to access the physical memory. Let Cache Hit ratio be H, Given, Access time of main memory = Amain = 6.0 ns Access time of cache memory =. Windows)). By clicking Post Your Answer, you agree to our terms of service, privacy policy and cookie policy. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. Question It is given that effective memory access time without page fault = i sec, = (1 / k) x { i sec + j sec } + ( 1 1 / k) x { i sec }. 80% of time the physical address is in the TLB cache. The total cost of memory hierarchy is limited by $15000. It is a question about how we translate the our understanding using appropriate, generally accepted terminologies. ____ number of lines are required to select __________ memory locations. nanoseconds) and then access the desired byte in memory (100 Your answer was complete and excellent. It is a question about how we interpret the given conditions in the original problems. This is better understood by. Main memory access time is 100 cycles to the rst bus width of data; after that, the memory system can deliv er consecutiv e bus widths of data on eac h follo wing cycle. But it hides what is exactly miss penalty. Follow Up: struct sockaddr storage initialization by network format-string, Short story taking place on a toroidal planet or moon involving flying, Bulk update symbol size units from mm to map units in rule-based symbology, Minimising the environmental effects of my dyson brain. Note: This two formula of EMAT (or EAT) is very important for examination. The mains examination will be held on 25th June 2023. Answer: If we fail to find the page number in the TLB then we must Practice Problems based on Page Fault in OS. 2. Block size = 16 bytes Cache size = 64 What is the main memory access takes (in ns) if Effective memory Access Time (EMAT) is 140ns access time? Integrated circuit RAM chips are available in both static and dynamic modes. But, the data is stored in actual physical memory i.e. In TLB a copy of frequently accessed page number and frame no is maintained which is from the page table stored into memory. nanoseconds), for a total of 200 nanoseconds. Browse other questions tagged, Start here for a quick overview of the site, Detailed answers to any questions you might have, Discuss the workings and policies of this site. It can easily be converted into clock cycles for a particular CPU. But it is indeed the responsibility of the question itself to mention which organisation is used. Does Counterspell prevent from any further spells being cast on a given turn? Average memory access time is a useful measure to evaluate the performance of a memory-hierarchy configuration. A direct-mapped cache is a cache in which each cache line can be mapped to only one cache set. If TLB hit ratio is 60% and effective memory access time is 160 ns, TLB access time is ______. Split cache : 16 KB instructions + 16 KB data Unified cache: 32 KB (instructions + data) Assumptions Use miss rates from previous chart Miss penalty is 50 cycles Hit time is 1 cycle 75% of the total memory accesses for instructions and 25% of the total memory accesses for data The result would be a hit ratio of 0.944. Staging Ground Beta 1 Recap, and Reviewers needed for Beta 2, How To Calculate Process Size from TLB size and mean memory access time, Relation between cache and TLB hit ratios. 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The fraction or percentage of accesses that result in a hit is called the hit rate. It takes 20 ns to search the TLB and 100 ns to access the physical memory. If you make 100 requests to read values from memory, 80 of those requests will take 100 ns and 20 of them will take 200 (using the 9th Edition speeds), so the total time will be 12,000 ns, for an average time of 120 ns per access. Which has the lower average memory access time? It is given that one page fault occurs every k instruction. The expression is somewhat complicated by splitting to cases at several levels. rev2023.3.3.43278. (I think I didn't get the memory management fully). Not the answer you're looking for? has 4 slots and memory has 90 blocks of 16 addresses each (Use as What is actually happening in the physically world should be (roughly) clear to you. Calculating effective address translation time. Here hit ratio =80% means we are taking0.8,TLB access time =20ns,Effective memory Access Time (EMAT) =140ns and letmemory access time =m. To get updated news and information subscribe: 2023 MyCareerwise - All rights reserved. Where TLB hit ratio is same single level paging because here no need access any page table, we get page number directly from TLB. (ii)Calculate the Effective Memory Access time . How many 128 8 RAM chips are needed to provide a memory capacity of 2048 bytes? 2- As discussed here, we can calculate that using Teff = h1*t1 + (1-h1)*h2*t2 + (1-h1)*(1-h2)*t3 which yields 24. Example 5:Here calculating memory access time, where EMAT, TLB access time, and the hit ratio is given. (That means that the L1 miss p enalt y, assuming a hit in the L2 cac he, is 10 cycles.) EAT := TLB_miss_time * (1- hit_ratio) + TLB_hit_time * hit_ratio. - Memory-intensive applications that allocate a large amount of memory without much thought for freeing the memory at run time can cause excessive memory usage. effective access time = 0.98 x 120 + 0.02 x 220 = 122 nanoseconds. (By the way, in general, it is the responsibility of the original problem/exercise to make it clear the exact meaning of each given condition. So, if hit ratio = 80% thenmiss ratio=20%. 160 ns = 0.6 x{ T ns + 100 ns } + 0.4 x { T ns + (1+1) x 100 ns }, 160 ns = 0.6 x { T ns + 100 ns } + 0.4 x { T ns + 200 ns }, 160 ns = 0.6T ns + 60 ns + 0.4T ns + 80 ns, 0.6T ns + 0.4T ns = 160 ns 60 ns 80 ns. Can Martian Regolith be Easily Melted with Microwaves. Consider a paging hardware with a TLB. What is a word for the arcane equivalent of a monastery? To calculate a hit ratio, divide the number of cache hits with the sum of the number of cache hits, and the number of cache misses. * [PATCH 1/6] f2fs: specify extent cache for read explicitly @ 2022-12-05 18:54 ` Jaegeuk Kim 0 siblings, 0 replies; 42+ messages in thread From: Jaegeuk Kim @ 2022-12-05 18:54 UTC (permalink / raw) To: linux-kernel, linux-f2fs-devel; +Cc: Jaegeuk Kim Let's descrbie it's read extent cache. If it was a 3 level paging system, would TLB_hit_time be equal to: TLB_search_time + 3* memory_access_time and TLB_miss_time be TLB_search_time + 3*(memory_access_time + memory_access_time) and EAT would then be the same? Because it depends on the implementation and there are simultenous cache look up and hierarchical. Write Through technique is used in which memory for updating the data? 2003-2023 Chegg Inc. All rights reserved. Calculating Effective Access Time- Substituting values in the above formula, we get- Effective Access Time = 0.8 x { 20 ns + 100 ns } + 0.2 x { 20 ns + (3+1) x 100 ns } = 0.8 x 120 ns + 0.2 + 420 ns = 96 ns + 84 ns = 180 ns Thus, effective memory access time = 180 ns. No single memory access will take 120 ns; each will take either 100 or 200 ns. EAT := (TLB_search_time + 2*memory_access_time) * (1- hit_ratio) + (TLB_search_time + memory_access_time)* hit_ratio. Since "t1 means the time to access the L1 while t2 and t3 mean the (miss) penalty to access L2 and main memory, respectively", we should apply the second formula above, twice. Why are physically impossible and logically impossible concepts considered separate in terms of probability? Practice Problems based on Multilevel Paging and Translation Lookaside Buffer (TLB). [for any confusion about (k x m + m) please follow:Problem of paging and solution]. Is it plausible for constructed languages to be used to affect thought and control or mold people towards desired outcomes? The cache access time is 70 ns, and the By clicking Post Your Answer, you agree to our terms of service, privacy policy and cookie policy. Now, substituting values in the above formula, we get-, = 10-6 x { 20 ns + 10 ms } + ( 1 10-6 ) x { 20 ns }, Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access takes 1 microsecond. 80% of the memory requests are for reading and others are for write. The TLB hit ratio is 90% and the page fault rate is one in every 10,000 instructions. (A) 120(B) 122(C) 124(D) 118Answer: (B)Explanation: TLB stands for Translation Lookaside Buffer. level of paging is not mentioned, we can assume that it is single-level paging. However, that is is reasonable when we say that L1 is accessed sometimes. Actually, this is a question of what type of memory organisation is used. Assume that Question Using Direct Mapping Cache and Memory mapping, calculate Hit Ratio and effective access time of instruction processing. I will let others to chime in. Number of memory access with Demand Paging. Ltd.: All rights reserved. The following equation gives an approximation to the traffic to the lower level. Assume no page fault occurs. Where: P is Hit ratio. Memory Stall Clock-cycles = ( Memory Access/Program ) X Miss Rate X Miss Penalties Memory Stall Clock-cycles = (Instructions/Program ) X ( Misses/Instructions ) X Miss Penalties Measuring and Improving Cache Performance : 1. There is nothing more you need to know semantically. If Effective memory Access Time (EMAT) is 140ns, then find TLB access time. The CPU checks for the location in the main memory using the fast but small L1 cache. Site design / logo 2023 Stack Exchange Inc; user contributions licensed under CC BY-SA. Asking for help, clarification, or responding to other answers. The cache access time is 70 ns, and the time for transferring a main memory block to the cache is 3000 ns. That would be true for "miss penalty" (miss time - hit time), but miss time is the total time for a miss so you shouldn't be counting the hit time on top of that for misses. Thus it exist a percentage of occurrences we have to include at least: Thanks for contributing an answer to Stack Overflow! Are those two formulas correct/accurate/make sense? Consider a paging system, it takes 10ns to search translation lookaside buffer (TLB) and 80ns to access main memory. as we shall see.) It tells us how much penalty the memory system imposes on each access (on average). Which of the following control signals has separate destinations? Which of the above statements are correct ? When a system is first turned ON or restarted? = 0.8 x{ 20 ns + 100 ns } + 0.2 x { 20 ns + (3+1) x 100 ns }. Does Counterspell prevent from any further spells being cast on a given turn? Let us use k-level paging i.e. If Cache has 4 slots and memory has 90 blocks of 16 addresses each (Use as much required in question). For example,if we have 80% TLB hit ratio, for example, means that we find the desire page number in the TLB 80% percent of the time. The percentage of times that the required page number is found in theTLB is called the hit ratio. It only takes a minute to sign up. A single-level paging system uses a Translation Look-aside Buffer (TLB) where memory access takes 100ns and hit ratio of TLB 80%. It looks like the solution depends on the definition of "the time to access the L1" and "the penalty to access L2 and main memory". The exam was conducted on 19th February 2023 for both Paper I and Paper II. Recovering from a blunder I made while emailing a professor. Learn more about Stack Overflow the company, and our products. If the page fault rate is 10% and dirty pages should be reloaded when needed, calculate the effective access time if: TLB Lookup = 20 ns TLB Hit ratio = 80% Memory access time = 75 ns Swap page time = 500,000 ns 50% of pages are dirty. A-143, 9th Floor, Sovereign Corporate Tower, We use cookies to ensure you have the best browsing experience on our website. = 120 nanoseconds, In the case that the page is found in the TLB (TLB hit) the total time would be the time of search in the TLB plus the time to access memory, so, In the case that the page is not found in the TLB (TLB miss) the total time would be the time to search the TLB (you don't find anything, but searched nontheless) plus the time to access memory to get the page table and frame, plus the time to access memory to get the data, so, But this is in individual cases, when you want to know an average measure of the TLB performance, you use the Effective Access Time, that is the weighted average of the previous measures. The average access time of the system for both read and write requests is, TPis the access time for physical memory, = (0.8 200 + 0.2 1000) nsec = 360 nsec. Paging in OS | Practice Problems | Set-03. Effective access time is a standard effective average. A place where magic is studied and practiced? Effective memory Access Time (EMAT) for single-level paging with TLB hit and miss ratio: EMAT for Multi-level paging with TLB hit and miss ratio: From the above two formulaswe can calculate EMAT, TLB access time, hit ratio, memory access time. The static RAM is easier to use and has shorter read and write cycles. 170 ns = 0.5 x{ 20 ns + T ns } + 0.5 x { 20 ns + (1+1) x T ns }, 170 ns = 0.5 x { 20 ns + T ns } + 0.5 x { 20 ns + 2T ns }. Problem-04: Consider a single level paging scheme with a TLB. the CPU can access L2 cache only if there is a miss in L1 cache. It follows that hit rate + miss rate = 1.0 (100%). For example, if you have 51 cache hits and three misses over a period of time, then that would mean you would divide 51 by 54. The cache has eight (8) block frames. Effective Access Time With Page Fault- It is given that effective memory access time without page fault = 20 ns. In the case that the page is found in the TLB (TLB hit) the total time would be the time of search in the TLB plus the time to access memory, so, TLB_hit_time := TLB_search_time + memory_access_time, In the case that the page is not found in the TLB (TLB miss) the total time would be the time to search the TLB (you dont find anything, but searched nontheless) plus the time to access memory to get the page table and frame, plus the time to access memory to get the data, so, TLB_miss_time := TLB_search_time + memory_access_time + memory_access_timeBut this is in individual cases, when you want to know an average measure of the TLB performance, you use the Effective Access Time, that is the weighted average of the previous measures. What will be the EAT if hit ratio is 70%, time for TLB is 30ns and access to main memory is 90ns? The logic behind that is to access L1, first. As both page table and page are in physical memoryT(eff) = hit ratio * (TLB access time + Main memory access time) +(1 hit ratio) * (TLB access time + 2 * main memory time)= 0.6*(10+80) + (1-0.6)*(10+2*80)= 0.6 * (90) + 0.4 * (170)= 122, This solution is contributed Nitika BansalQuiz of this Question. Does a barbarian benefit from the fast movement ability while wearing medium armor? | solutionspile.com Consider a single level paging scheme with a TLB. We can write EMAT formula in another way: Let, miss ratio = h, hit ration = (1 - h), memory access time = m and TLB access time = t. So, we can write Note: We can also use this formula to calculate EMAT but keep in your mind that here h is miss ratio. Outstanding non-consecutiv e memory requests can not o v erlap . Then the value of p is-, 3 time units = px { 1 time unit + p x { 300 time units } + (1 p) x { 100 time units } } + (1 p) x { 1 time unit }, 3 = p x { 1 + 300p + 100 100p } + (1 p), On solving this quadratic equation, we get p = 0.019258. Get more notes and other study material of Operating System. To find the effective memory-access time, we weight the case by its probability: effective access time = 0.80 100 + 0.20 200 = 120 nanoseconds but in the 8th edition of the same book I'm confused with the effective access time Can someone explain it for me? In this article, we will discuss practice problems based on multilevel paging using TLB. Assume that the entire page table and all the pages are in the physical memory. What's the difference between cache miss penalty and latency to memory? So, how many times it requires to access the main memory for the page table depends on how many page tables we used. Experts are tested by Chegg as specialists in their subject area. In Virtual memory systems, the cpu generates virtual memory addresses. Using Direct Mapping Cache and Memory mapping, calculate Hit We can solve it by another formula for multi-level paging: Here hit ratio = 70%, so miss ration =30%. The dynamic RAM stores the binary information in the form of electric charges that are applied to capacitors. Arwin - 23206008@2006 1 Problem 5.8 - The main memory of a computer is organized as 64 blocks with a block size of eight (8) words. Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds and servicing a page fault takes 8 milliseconds. Regarding page directory (the first level of paging hierarchy) I believe it has to be always resident in RAM (otherwise, upon context switch, the x86 CR3 register content would be totally useless). Effective memory Access Time (EMAT) for single-level paging with TLB hit ratio: Here hit ratio (h) = 80% means here taking 0.8, memory access time (m) = 80ns and TLB access time (t) = 10ns. Effective access time is increased due to page fault service time. average time) over a large number of hits/misses will be 0.8 * (hit time) + 0.2 * (miss time). Thanks for contributing an answer to Stack Overflow! There are two types of memory organisation- Hierarchical (Sequential) and Simultaneous (Concurrent). Principle of "locality" is used in context of. A TLB-access takes 20 ns and the main memory access takes 70 ns. Ratio and effective access time of instruction processing. Thanks for the answer. a) RAM and ROM are volatile memories This increased hit rate produces only a 22-percent slowdown in access time. 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